computer organization and architecture - due in 8-9 hours

Computer Organization and Architecture

ASSIGNMENT:

1. The following MIPS code calculates the floating-point expression E = A * B + C * D, where the addresses of A, B, C, D, and E are stored in R1, R2, R3, R4, and R5, respectively:

L.S F0, 0(R1) L.S F1, 0(R2) MUL.S F0, F0, F1

L.S F2, 0(R3) L.S F3, 0(R4) MUL.S F2, F2, F3

ADD.S F0, F0, F2

S.S F0, 0(R5)

Rewrite the code sequence, but now using only two floating-point registers. Optimize for minimum run-time. You may need to use temporary memory locations to hold intermediate values. List the code sequence and give the number of cycles this takes to execute.

2. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Show how you arrive at your answer.

Instruction Meaning of instruction

I0 :MUL R2 ,R0 ,R1 R2 ← R0 *R1

I1 :DIV R5 ,R3 ,R4 R5 ← R3 /R4

I2 : ADD R2 ,R5 ,R2 R2 ← R5 + R2

I3 :SUB R5 ,R2 ,R6 R5 ← R2 - R6