electronic 2 lab

EXPERIMENT #10 CMOS OP AMPS I OBJECTIVES The objective of this Experiment is twofold; to provide insights into the structure of basic two-stage cMos amplifiers, ancl to provide expericncc with larger-systelns applications using a relatively large nurnber of CMOS dcvice arrays.

U COMPONBNTS AND INSTRUMENTATION The primary requirement is for three CD4007 CMOS array ICs.

Up to four additional cD4007 can bc used for optional enrichment explorations. As well, you neecl a lood collection of capacitors ranging from l0 pF to 0'lpF in a 0.1,0'33 sequence, a low-inductance low-leakale (ceramic) capacitor of at least lpF as well as power-supply bypass capacitors.

As for equipment, you need a dual power suiply, DMM, waveform genera- tor and dual-channel oscilloscope.

As well, a capacitoi box having 4 or more decades would be useful, though not essential.

For convenience, Fig. l0,l provides various views of the cD4007 package.

JJLJ r 1 | '-r-J | '-,J dq .L,gt l-1=l n,J' '._}Jl | '-r | | '-t a..aaaa 7 g 3 4 5 ro g El {$ {$_ql Views of the CD4007 MOS Array package III READING Concentration will be on Sections 10.7 and 10.8 of the Text. Familiarity with Mos devices and particu- larly part of Section 5'7 on CMOS is assumed.

Reference will also be made to material on pulse circuits in the latter part of Appendix F of the Text, and to aspects of feedback including resistance mod'ification in Section 8.2, and pole splitting in Section 8.11.

(a) (b) IV PREPARATION Following the usual pattern in this Manual, Preparation tasks are keyed directly to the Explorations to follow, by the use of the same titling and section nurnbering, augmented by the prefix p.

Note that there are a large number of preparations here, some of considerable compl"xity.

Clearly, not all can be quickly done. But neither can all of the Explorations!

The challenge for you here is to seleci some of the suggested preparatory investigations to work on. They are very informative, but also time consumins.

Figure I0.l -93- Experiment #10-2 . THE BASIC AMPLIFIER P1.1 DC Operation (a) Consider thc cMos amplificr i1 Fig. 10.2 employing transisrors for which lv,l = lv,,t = 0.50 mA./V, and l" = l/50V.

For + 7.5 V supplies, Ri= 22OkA, Vr = Vs, and Va = Oy, estimate all node voltages and device curronts, assuming the eflect of l, to U" n"gflgiUl".

(b) Now, estimate ro for each device and the change in bias current that implies.

(d) For the bias situation idcntificcl in (a) above, fincJ g,n for each clevice.

(e) using the value of ro estimated in (b) and of g,, in (d), estimate thc open-loop gain of the amplifier DJhoo.

. AC UNITY.GAIN OPERATION Pz.L over-compensated operation with a Dominant Load pole (a) Consider the circuit of Fig.

10.2 in which R2 =q, C2 = b and for which nodes F ancl B are joined, with a load capacitance, Cr = 0.

lpF, connected from node F to ground.

Estimate its output slew rate -for large positive-going and negative-going inputs for which one of ero or e2 is cut off' AIso find an approximation to the corresponclin g lTVo to 90% risc and fall times.

(b) Using the values of open-loop output resistance and gain idenrified in pl.l (b) ancl (e), with the relevant value of feedback B, estimate (roughly) the gain and output resistance of thc closed loop.

P2,2 Minimal Load-Capacitance Compensation (a) consider tlre circuit of Fig.

10.2 as an open-loop amplifier with a loacl capacitance c1 = g.lpF.

Assume that the amplilier's dynamics are controlled by the output pole and the Miller-Effecr influenced pole at the gate of Qoc, whose C*z is perhaps 2pF, and for which wiring capacitance at node E is possibly l5pF. Estimare the two poles.

(b) Prepare a corresponding Bocle magnitude plot of open-loop gain, on which a line for 0 = I is included. comment on the stabirity of the corresponding cloiea roop.

P2.3 Internal Compensation (a) Consider the situation in which the output capaciror at node F of Fig. 10.2 is reduced to l00pF, for the conditions in which, for Q6s, Crr = 2pF, and Cr,ro, (due to wiring) at the gate and drain are perhaps l5pF each.

Using Eq. 10'49 and 10.50 of thc Text, esimate the location of the corresponding poles.

(b) Prepare a corresponding Bode magnitude plot on which a line for F = I is included.

Cornment on stability.

(c) For the situation investigated above, to what frequcncy must the lower pole be movccl to ensure stability witlr 45' phase margin? with 65. phase rnargin?

. HIGHER.GAIN OPERATION P3.1 An Amplifier with Gain of +100 V/V (a) For the amplifier of Fig.

10.2 as analyzed in the Preparations above, embedclcd in the 100 kCl- lOkO loop described in 83.1, what closed-loop gain results?

P3.2 Open-Loop Gain (a) sketch the circuit described inE3.2, using a triangular amplifier symbol. calculate the open-loop gain of the amplifier as detailed earlier, which applies at very-low and relatively-high frequencies.

-94- _7 50 all of he lre )ut ;ut he ct- at is .or tre he ;)- 0p -95- (b) on a Bode.magnitude plot of ofi:lo?.p gain, using rhe low-frequency value found in (a), w poles as estimated in P2.3 (a) {aclmitte<.liy iuitt, o ,*itt'-iooa "upo"iror, a fact we wi, ignore herr lffJ,j,ffi;"ffiff:iTii"",lll"ltTi;o,rn;;;Ack network.

co,nn,",,i on stabliry.

wr . EFFECTS OF DEVICE SIZING P4.1 Many possibilities (a) For one or more of the revised circuits.(a), (b), (c) (or any combination) alludcd to in E4.1, find tl corresponding bias currents and open-loop gain, uring rt'," conditions prcscnted in pl.1 (a) abov and ignoring the effects associated with 1,.

. THE BASIC AMPLIFIDR Experiment #l( V EXPLORATION The basic amplilier on which.you will experiment resembles the two-stage topology shown in Fig.

10.2 of the Text' This is depicted herc u, *"11, in rig. 10.2.

Note o rolo.

differcnce here is that choice r device ratios is limitecl by virtue of arrav;""t;;;;i,rr.'?tu"ii" rrre amprifier w'r be srabitizcd fc low-frequency operation by a large loaa capacitor.

9^t Figure 10'2A Basic Two'stage.

cMos op Amp. Tttree CD4007 arrays (A,B,C) are required" Pin nuntbers are for the corresponding'prackage.

Note the 6 substrate cotutectiotts, wltich are essential for correct operation of tne iiays E1.1 DC Operation . Goal:

To verify the DC operation of the assembled CMOS op amp.

. Setup:

O Assemblethecircuitshown,.n.Fis.

l0.2using*7.5Vsupplies, Rt=220kd1,R2=e,Brd cz=0 pF' connect the positive input (A) tJground, the negative input (a) to the output (F), and a capacitor Cr = 0.1lrF from outpur (i) to grounA.

. Measurement:

a) with zero input voltage, verify that thc amplilier is stable by measuring first node F. and then node E with your oscilloscope, using a xl0 probe. "l_ ".

T"' t= @o ?' V @r Experiment #10-4 b) Using your DVM with a series l0 k(t resistor as a probc (to minimize various effects of the meter leads), measure (some of the) dc voltages at nodcs A through G.

. Tabulation:

Va, Va, Vc, VD, Vg, Vp, V6, . Analysis:

consider the offset voltage you have found.

over what range of input voltages would you expect the output to follow the input rcasonably wcll?

E1.2 Evaluating the Linear Operating Range . Goal:

To investigate the rangc of (lincar) operation of the amplifier as bias currcnt changes.

. Setup:

O Connect the positive input.(A) to the ccnter-tap of a 10 kC), potentiometer (R1) whose encls are connected to the positive and negative supplies. The negative input (a) remains con- nected to the output (F).

. Measurement:

a) While measuring the offset voltage clirectly (between nodes A and B), with your DVM, use R3 to raise and lower the voltagc on node A . For thc two settings of pot Rr at which the offset changes by 0.1 V from its micl-level value, rneasure tlre vJtages at nodes A, B (and others as you see fit).

b) Repeat the previous step with R1 shunted by a resistor, R4, of equal valuc. In particular, note the offsct voltage for V1 = 0, and the voltages at nodcs A tlrrough G at which the offset changcs by 0.1 V, and by 0.2y.

. Tabulation:

R t, Veo , VA, VB , and others, for interesting values of V1 using two offset thresholds.

. Analysis:

Consider the fact that the change in offset voltage at the extremes of input voltage represents the edge of linear operation for large input signals. Try to identify the parr of ttre circui at which the critical nonlinearity occurs.

. AC UNITY.GAIN OPERATION Ez.l over-compensated operation with a Dominant Load pole . Goal:

To explore the amplifier's operating clynamics.

. Setup:

O Assemble the circuit of Fig. 10.2 as inclicated in Exploration El.l above, but with inputA connected to a waveform generator (node /), via a resistor, Rs = l0 kO.

-96- Experimert #10-5 . Mcasurement:

a) Using your (nonnalized) dual-channel oscilloscope, and a 4 Vpp input square wave at 100 Hz, compare the waveforms at A and F.

What are the relativc amplitudest What are the times taken for 50vo of the total output change? for a change ftcrrn lyvo to 90Zo of the final output? Sketch the waveforms at A and F.

b) With input A shunted to ground with a l00o resistor, rcpeat thc previous msasurclnents [with an input signal about l%o as large as before].

c) With conditions othcrwise the satne as in stcp b), change the generator input to a sine wave and lneasure the voltage gain by cornparing peak-to-peak values. Now, raise the input frequency until the gain is 0.707 of its lower-frequeniy value (that is, until it has dropped by 3dB).

. Tabulation:

UA,1)F, tSO, lg0,t:u,,O1 ,f .

. Analysis:

Considcr the operation of the circuit as a followcr, including estimates of its gain, slew rate, ancl large- and small-signal bandwidths.

Use the relationships in Appendix E of thJ Tcxt, in particular cquation (8.

l3), to relate rise-times and bandwidths.

82.2 Minimal Load-Capacitance Compensation 'Goal: To explore the elfects of moving to more minimal compensation.

' SetuP:

O Use the circuit of Fig.

10.2 as connected in steps b) ancl c) of Explora tion E2.l above. As well, in preparation for the next step, shunt the load capacitor, Ct - 0.lpF, by a second capacitor' Cro = l00pF, wired with very short leads from output F to ground.

. Measurement:

a) With a 4Vpp square wave at l00Hz applied at tlre input, note the output waveform in some detail, particularly at the times following slewing wherc linear operation begins (and continues), b) Replace C1 by a capacitor decade box set to 0. lpF.

Again observe the output, For a rea- sonable box and relatively short connections, you can expect the waveforms to be quite sirnilar to those found previously.

If not, you will have to use a selection of discrete capa- citors in what follows.

c) With a 0'lVpp square wave at 100 Hz at node.4, and xlO probes at nodes A, F, reduce the primary load capacitance Cl until a peaked oscillatory response is seen at F. Choose a value of C1 for which the overshoot is some reasonable value (say lO to 2OVo), Note the value of C1 (including the small capacitor Cle). Call it Cn. (To be somewhat consistcnt, let C11 = 0.lpF be the original value of C1.) . Tabulation:

Overshoot, C12.

-97 - Experiment #10-6 . Analysis:

Consider the possible improvcment in dynamics you can expect. By what factor will the slew rate change?

[,2,3 Internal Compensation . Goal:

To explore the possibility of internal-feedback compensation.

' SetuP:

O Use the test setup as established in the last step of E2.2. With Cl2 connected as a combi- nation of discrete capacitors, install R2 and C2 as shown in the circuit of Fig. 10.2.

Select R2 initially largc (say Reo = 100 kC)), with C2 initially small (say Czo = 10 pF)' . Measurement:

a) Display nodss A and F using lOx probes.

Incrcase C2 fromC2s to C21, a value at which the overshoot at F rcduces by 20 to 30Vo or so from thc value established in the last step of E2.2.

b) With Ct = Cn and Cz= Czr, reduce Rz (by shunting) from R2e until the overshoot is minimized, at R2 = ftrt.

c) With C1 = Ct2, Cz= Czr and R2 = Rzr initially, changc C1 from Ceto Cp for which the overshoot is again as large as it was at the end of the last step of 82.2.

d) Change C2 from C21 to C22 in an attempt to reduce the overshoot once more. Then, change R2 to R2y and C2 again, itcratively, to reduce the overshoot. Call the values finally chosen C s, Cy and R23, for convenience.

e) Now, if time pennits, evaluate the effect of changing C1 from C13, particularly as it is increased.

0 Now, with the input changed to a O.lVpp sine wave, initially at 100 Hz, raise the fre- quency until the gain falls to 0.707 of its low-frequency valuc, noting any voltage peaks along the way.

. Tabulation:

Cr, Cz, R2, overshoot, in many combinations leading ideally to small C1 and small overshoot.

. Analysis:

Consider the virtues and deficiencies of the unity-gain stabilization process you have just gone through.

. HIGHER-GAIN OPERATION E3.1 An Amplifier with a Nominal Gain of +1,00 . Goal:

To evaluate operation at increased gain.

' SetuP:

O Connect the circuit of Fig. 10.2 with 17.5 V supplies, Rr =220k{1, R2= Rzr = 100 kO, Cz= Czt, and load capacitance Cr= CB, or C1 = Cz = l00pF, if in doubt. Externally, connect a feedback network from node F to node B consisting of a lOOkCt feedback -98- Expertment #10-7 I rcsistor and I kO to ground, with a l00kQ, lkCl input-signal divider (with the lkg grounded) connected to the positivc amplifier input (A) fiom tlie gencrator (1).

. Measurement:

a) Adjust a square-wave inplt at l00Hz to provide an output of lV pp.

Measure the peak- to-peak voltage at nodes F and A in order to estimate the closed-loop gain.

b) Note the output overshoot' Remove thc load capacitor (C1), ancl note the overshoot again.

. Tabulation:

Cl, UA, DF, oversho0t.

. Analysis:

Consider your estimate of thc closed-loop gain, Notc, as wc shall verify shortty, that its valuc is affected by the rcsistance level of the feeclback network. Note also that the loop is more easily stabil- ized for nominal gains >>r. what evidence do you have for this?

83.2 Open-loop Gain . Goal:

To measure the open-loop gain by introducing cxternal dominant-pole compensation.

. Setup:

O Connect the circuit of Fig. 10.2 as described in 83.1 setup, with an input attenuator as indicated, but with a feedback network consisting of a lOMCtresistorRT irom output F to the negative input.B, and a large low_leakagc capacitor (C:

= l0 pF, tantalum) from B to ground.

Use a sinewave input initially at 10 kHz.

. Measurement:

a) Adjust the input for an ourpur of I V pp at F.

b) vary the frequency, and note the upper ancl lower 3dB frequencies.

c) Assuming a midband region of at least a frequency clecacle, Ineasure the midband gain. (If the midband is seen to be very narrow, R1 or c7 must be increased.) d) Repeat all of.the previous three steps with a resistor R7 = IMO connected from the output directly to ground.

(If the output offset is targe, use a capacitor of 0.lpF in scries with Rr,.) c) Repeat the entire three-step process again with Rr = l00kC).

. Tabulation:

RL, D, D1 , f y , /1 with RL = -, I MQ and 100 kfl.

. Analysis:

Consider the open-loop gain you have founcl, and its clependence on load resistance.

Consicler also the dependence of the low-frequency cutoff on the value of Rr as it affects the resistance seen by C3 [See section 8.2 of the Text], -99 - Experiment #10-8 . EFFECTS OF DBVICE SIZING 84.1 Many Possibilities While there is limitcd flexibility avaitable in the control of devicc sizes when using arrays, one possibility exists' In general, it is to directly parallel array colnponents.

The primary pr""ouiion to take is to ensure that both the p-channel and n-channel substratet or" uppropriately conneci.i 1to the +ve and -ve supplies respectively).

several interesting possibirities for parallel connection exist:

(a) Paralleling Q1s and e26, with components from a fourth array; (b) Parallcling 0rc and 946, with components from a fifth array; (c) Paralleling Qla and Q66', with components from 2 additional arrays (arrays numbered 4,5 (or 6,7 if 4, 5 are already employed in a), b))).

While essentially any of thc precccling Explorations can bc rcpeatccl with suclr changcs, th

obviously, there are a great many possibilities!

CMOS Op'Amps _are increasingly important in analog signal-processing systems implemented in Very Large Scale Integration (VLSI).

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