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An IMPORTANT NOTICEatthe end ofthis data sheet addresses availability, warranty,changes,useinsafety-critical applications, intellectual propertymattersandother important disclaimers. PRODUCTION DATA.

TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 TLC555 LinCMOS ™Timer 1 1 Features 1 • Very LowPower Consumption:

– 1mW Typical atV DD = 5V • Capable ofOperation inAstable Mode • CMOS Output Capable ofSwinging RailtoRail • High Output Current Capability – Sink: 100mATypical – Source: 10mA Typical • Output FullyCompatible WithCMOS, TTL,and MOS • Low Supply Current Reduces SpikesDuring Output Transitions • Single-Supply OperationFrom2V to 15 V • Functionally Interchangeable WiththeNE555; Has Same Pinout • ESD Protection Exceeds2000VPer MIL-STD- 883C, Method 3015.2 • Available inQ-Temp Automotive – High-Reliability AutomotiveApplications – Configuration ControlandPrint Support – Qualification toAutomotive Standards 2 Applications • Precision Timing • Pulse Generation • Sequential Timing • Time Delay Generation • Pulse Width Modulation • Pulse Position Modulation • Linear RampGenerator Simplified Schematic 3 Description The TLC555 isamonolithic timingcircuitfabricated using theTILinCMOS ™process. Thetimer isfully compatible withCMOS, TTL,andMOS logic, and operates atfrequencies upto2MHz. Because ofits high input impedance, thisdevice usessmaller timing capacitors thanthose usedbythe NE555. Asa result, moreaccurate timedelays andoscillations are possible.

Powerconsumption islow across thefull range ofpower-supply voltage.

Like theNE555, theTLC555 hasatrigger levelequal to approximately one-thirdofthe supply voltage anda threshold levelequal toapproximately two-thirdsof the supply voltage. Theselevelscanbealtered by use ofthe control voltage terminal (CONT). Whenthe trigger input(TRIG) fallsbelow thetrigger level,the flip-flop isset and theoutput goeshigh.IfTRIG is above thetrigger levelandthethreshold input (THRES) isabove thethreshold level,theflip-flop is reset andtheoutput islow. Thereset input(RESET) can override allother inputs andcanbeused to initiate anew timing cycle.IfRESET islow, theflip- flop isreset andtheoutput islow. Whenever the output islow, alow-impedance pathisprovided between thedischarge terminal(DISCH) andGND.

All unused inputsmustbetied toan appropriate logic level toprevent falsetriggering.

Device Information (1) PART NUMBER PACKAGE BODY SIZE(NOM) TLC555C SOIC (8) 4.9 mm ×3.91 mm PDIP (8) 9.81 mm×6.38 mm SOP (8) 6.20 mm×5.30 mm TSSOP (14) 5.00 mm×4.40 mm TLC555I SOIC (8) 4.90 mm×3.91 mm PDIP (8) 9.81 mm×6.38 mm TLC555M LCCC (20) 8.89 mm×8.89 mm CDIP (8) 9.60 mm×6.67 mm TLC555Q SOIC (8) 4.90 mm×3.91 mm (1) For allavailable packages, seetheorderable addendum at the end ofthe data sheet. R1 R S1 THRES R R R TRIG 2 1 GND DISCH 7 3 OUT 6 V DD 8 5 CONT RESET 4 Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design 2 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Table ofContents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Device Comparison Table..................................... 3 6 PinConfiguration andFunctions ......................... 3 7 Specifications ......................................................... 6 7.1 Absolute Maximum Ratings...................................... 6 7.2 Recommended OperatingConditions ....................... 6 7.3 Thermal Information .................................................. 6 7.4 Electrical Characteristics: V DD = 2V for TLC555C, V DD = 3V for TLC555I ............................................... 7 7.5 Electrical Characteristics: V DD = 5V......................... 8 7.6 Electrical Characteristics: V DD = 15 V..................... 11 7.7 Electrical Characteristics: V DD = 5V ...................... 14 7.8 Typical Characteristics ............................................ 14 8 Detailed Description ............................................ 15 8.1 Overview ................................................................. 15 8.2 Functional BlockDiagram ....................................... 15 8.3 Feature Description ................................................. 15 8.4 Device Functional Modes........................................ 19 9 Application andImplementation ........................20 9.1 Application Information............................................ 20 9.2 Typical Applications ................................................ 20 10 Power Supply Recommendations .....................26 11 Layout ................................................................... 27 11.1 Layout Guidelines ................................................. 27 11.2 Layout Example .................................................... 27 12 Device andDocumentation Support................. 28 12.1 Receiving Notification ofDocumentation Updates28 12.2 Community Resources.......................................... 28 12.3 Trademarks ........................................................... 28 12.4 Electrostatic DischargeCaution............................ 28 12.5 Glossary ................................................................ 28 13 Mechanical, Packaging,andOrderable Information ........................................................... 28 4 Revision History Changes fromRevision G(November 2008)toRevision H Page • Added Feature Description section,DeviceFunctional Modes,Application andImplementation section,Power Supply Recommendations section,Layoutsection, DeviceandDocumentation Supportsection,andMechanical, Packaging, andOrderable Information section..................................................................................................................... 1 • Deleted Continuous totalpower dissipation andlead temperature parametersfromAbsolute Maximum Ratings............... 6 • Changed valuesinthe Thermal Information tabletoalign withJEDEC standards. ............................................................... 6 • Deleted Dissipation Ratingstable.......................................................................................................................................... 6 3 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated 5 Device Comparison Table DEVICE T A V DD RANGE SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) SSOP (PS) TSSOP (PW) TLC555C 0 °C to 70°C 2 V to 15 V ✓ — — ✓ ✓ ✓ TLC555I – 40 °C to 85°C 3 V to 15 V ✓ — — ✓ — — TLC555M – 55 °C to 125 °C 5 V to 15 V — ✓ ✓ — — — TLC555Q – 40 °C to 125 °C 5 V to 15 V ✓ — — — — — 6 Pin Configuration andFunctions TLC555C:

D,P,and PSPackages 8-Pin SOIC, PDIP,SOP Top View TLC555C:

PWPackage 14-Pin TSSOP Top View Pin Functions: TLC555C PIN I/O DESCRIPTION NAME SOIC, PDIP, SOP TSSOP CONT 5 8 I Controls comparator thresholds.Outputs2/3V DD and allows bypass capacitor connection.

DISCH 7 12 O Open collector outputtodischarge timingcapacitor GND 1 1 Ground NC — 2, 4,6, 9, 11, 13 — No internal connection OUT 3 5 O High current timeroutput signal RESET 4 7 I Active lowreset inputforces output anddischarge low THRES 6 10 I End oftiming input.THRES >CONT setsoutput lowand discharge low.

TRIG 2 3 I Start oftiming input.TRIG<½ CONT setsoutput highanddischarge open.

V DD 8 14 — Power-supply voltage1 234567 NC OUT NC RESET TRIG NC GND THRES NC CONT DISCH NC V DD NC 14 1312 11 10 98 GND TRIG DISCH THRES CONT OUT RESET 1 2 3 4 8 7 6 5 V DD 4 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated TLC555I:

Dand PPackages 8-Pin SOIC, PDIP Top View Pin Functions: TLC555I PIN I/O DESCRIPTION NAME SOIC, PDIP CONT 5 I Controls comparator thresholds.Outputs2/3V DD and allows bypass capacitor connection.

DISCH 7 O Open-collector outputtodischarge timingcapacitor GND 1 — Ground OUT 3 O High current timeroutput signal RESET 4 I Active lowreset inputforces output anddischarge low THRES 6 I End oftiming input.THRES >CONT setsoutput lowand discharge low.

TRIG 2 I Start oftiming input.TRIG<½ CONT setsoutput highanddischarge open.

V DD 8 — Power-supply voltageGND TRIG DISCH THRES CONT OUT RESET 1 2 3 4 8 7 6 5 V DD 5 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated TLC555M:

JGPackage 8-Pin CDIP Top View TLC555M:

FKPackage 20-Pin LCCC Top View Pin Functions: TLC555M PIN I/O DESCRIPTION NAME LCCC CDIP CONT 12 5 I Controls comparator thresholds.Outputs2/3V DD and allows bypass capacitor connection.

DISCH 17 7 O Open-collector outputtodischarge timingcapacitor GND 2 1 — Ground NC 1, 3,4,6,8, 9, 11, 13,14, 16, 18,19 — — No internal connection OUT 7 3 O High current timeroutput signal RESET 10 4 I Active lowreset inputforces output anddischarge low THRES 15 6 I End oftiming input.THRES >CONT setsoutput lowand discharge low.

TRIG 5 2 I Start oftiming input.TRIG<½ CONT setsoutput highanddischarge open.

V DD 20 8 — Power-supply voltage TLC555Q:

DPackage 8-Pin SOIC Top View Pin Functions: TLC555Q PIN I/O DESCRIPTION NAME SOIC CONT 5 I Controls comparator thresholds,Outputs2/3VDD, allows bypass capacitor connection DISCH 7 O Open-collector outputtodischarge timingcapacitor GND 1 — Ground OUT 3 O High current timeroutput signal RESET 4 I Active lowreset inputforces output anddischarge low THRES 6 I End oftiming input.THRES >CONT setsoutput lowand discharge low TRIG 2 I Start oftiming input.TRIG<½ CONT setsoutput highanddischarge open V DD 8 — Power supply voltageGND TRIG DISCH THRES CONT OUT RESET 1 2 3 4 8 7 6 5 V DD NCGND NC V DD NC 4 5 6 7 8 9 3 10 2 11 1 12 20 13 19 18 1716 15 14 NC NC DISCH NC THRES NC NC RESET NC CONT NC TRIGNC OUT NC GND TRIG DISCH THRES CONT OUT RESET 1 2 3 4 8 7 6 5 V DD 6 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated (1) Stresses beyondthoselistedunder Absolute Maximum Ratingsmaycause permanent damagetothe device. Thesearestress ratings only, which donot imply functional operationofthe device atthese orany other conditions beyondthoseindicated underRecommended Operating Conditions .Exposure toabsolute-maximum-rated conditionsforextended periodsmayaffect device reliability.

(2) Allvoltage valuesarewith respect tonetwork GND.

7 Specifications 7.1 Absolute Maximum Ratings over operating free-airtemperature range(unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, V DD (2) 18 V Input, anyinput − 0.3 V DD V Current Sink, discharge oroutput 150 mA Source, output,I O 15 mA Temperature Operating, T A C-suffix 0 70 ° C I-suffix – 40 85 ° C Q-suffix – 40 125 ° C M-suffix – 55 125 ° C Case, for60seconds FK package – 65 150 ° C Storage, T stg – 65 150 ° C 7.2 Recommended OperatingConditions over operating free-airtemperature range(unless otherwise noted) MIN MAX UNIT Supply voltage, V DD 2 15 V Operating free-air temperature, T A TLC555C 0 70 ° C TLC555I – 40 85 ° C TLC555M – 55 125 ° C TLC555Q – 40 125 ° C (1) Formore information abouttraditional andnew thermal metrics, seetheSemiconductor andICPackage ThermalMetricsapplication report.

7.3 Thermal Information THERMAL METRIC(1) TLC555 UNIT D (SOIC) FK (LCCC) JG (CDIP) P (PDIP) PS (SOP) PW (TSSOP) 8 PINS 20 PINS 8 PINS 8 PINS 8 PINS 14 PINS R θJA Junction-to-ambient thermalresistance 113 n/a 120 58 120 135 ° C/W R θJC(top) Junction-to-case (top)thermal resistance 58 37 81 48 72 61 ° C/W R θJB Junction-to-board thermalresistance 55 36 110 35 69 77 ° C/W ψ JT Junction-to-top characterization parameter 11 n/a 45 26 32 12 ° C/W ψ JB Junction-to-board characterization parameter 54 n/a 103 35 68 77 ° C/W R θJC(bot) Junction-to-case (bottom)thermal resistance n/a 4.3 31 n/a n/a n/a ° C/W 7 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated (1) Fullrange is0°C to 70°C the forTLC555C, and−40 °C to 85°C for the TLC555I. Forconditions shownasMax ,use theappropriate value specified inthe Recommended OperatingConditions table.

(2) These values applyforthe expected operating configurations inwhich THRES isconnected directlytoDISCH ortoTRIG.

7.4 Electrical Characteristics: V DD = 2V for TLC555C, V DD = 3V for TLC555I over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT V IT Threshold voltage 25 °C TLC555C 0.95 1.33 1.65 V TLC555I 1.6 2.4 Full range TLC555C 0.85 1.75 V TLC555I 1.5 2.5 I IT Threshold current 25 °C TLC555C 10 pA TLC555I 10 Max TLC555C 75 pA TLC555I 150 V I(TRIG) Trigger voltage 25 °C TLC555C 0.4 0.67 0.95 V TLC555I 0.71 1 1.29 Full range TLC555C 0.3 1.05 V TLC555I 0.61 1.39 I I(TRIG) Trigger current 25 °C TLC555C 10 pA TLC555I 10 Max TLC555C 75 pA TLC555I 150 V I(RESET) Reset voltage 25 °C TLC555C 0.4 1.1 1.5 V TLC555I 0.4 1.1 1.5 Full range TLC555C 0.3 2 V TLC555I 0.3 1.8 Control voltage (open-circuit) asa percentage ofsupply voltage Max TLC555C 66.7% TLC555I 66.7% Discharge switchon-stage voltage I OL = 1mA, 25°C TLC555C 0.03 0.2 V TLC555I 0.03 0.2 I OL = 1mA, Fullrange TLC555C 0.25 V TLC555I 0.375 Discharge switchoff-stage current 25 °C TLC555C 0.1 nA TLC555I 0.1 Max TLC555C 0.5 nA TLC555I 120 V OH High-level outputvoltage I OH = –300 µA, 25°C TLC555C 1.5 1.9 V TLC555I 2.5 2.85 I OH = –300 µA, Full range TLC555C 1.5 V TLC555I 2.5 V OL Low-level outputvoltage I OL = 1mA, 25°C TLC555C 0.07 0.3 V TLC555I 0.07 0.3 I OL = 1mA, Fullrange TLC555C 0.35 V TLC555I 0.4 I DD Supply current(2) 25 °C TLC555C 250 µ A TLC555I 250 Full range TLC555C 400 µ A TLC555I 500 8 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated (1) Fullrange is0°C to 70°C the forTLC555C, −40 °C to 85°C for the TLC555I, −40 °C to 125 °C for the TLC555Q, and−55 °C to 125 °C for the TLC555M. Forconditions shownasMax ,use theappropriate valuespecified inthe Recommended OperatingConditions table.

7.5 Electrical Characteristics: V DD = 5V over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT V IT Threshold voltage 25 °C TLC555C 2.8 3.3 3.8 V TLC555I 2.8 3.3 3.8 TLC555M 2.8 3.3 3.8 TLC555Q 2.8 3.3 3.8 Full range TLC555C 2.7 3.9 V TLC555I 2.7 3.9 TLC555M 2.7 3.9 TLC555Q 2.7 3.9 I IT Threshold current 25 °C TLC555C 10 pA TLC555I 10 TLC555M 10 TLC555Q 10 Max TLC555C 75 pA TLC555I 150 TLC555M 5000 TLC555Q 5000 V I(TRIG) Trigger voltage 25 °C TLC555C 1.36 1.66 1.96 V TLC555I 1.36 1.66 1.96 TLC555M 1.36 1.66 1.96 TLC555Q 1.36 1.66 1.96 Full range TLC555C 1.26 2.06 V TLC555I 1.26 2.06 TLC555M 1.26 2.06 TLC555Q 1.26 2.06 I I(TRIG) Trigger current 25 °C TLC555C 10 pA TLC555I 10 TLC555M 10 TLC555Q 10 Max TLC555C 75 pA TLC555I 150 TLC555M 5000 TLC555Q 5000 V I(RESET) Reset voltage 25 °C TLC555C 0.4 1.1 1.5 V TLC555I 0.4 1.1 1.5 TLC555M 0.4 1.1 1.5 TLC555Q 0.4 1.1 1.5 Full range TLC555C 0.3 1.8 V TLC555I 0.3 1.8 TLC555M 0.3 1.8 TLC555Q 0.3 1.8 I I(RESET) Reset current 25 °C TLC555C 10 pA TLC555I 10 TLC555M 10 TLC555Q 10 Max TLC555C 75 pA TLC555I 150 TLC555M 5000 TLC555Q 5000 9 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Electrical Characteristics: V DD = 5V (continued) over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Control voltage (opencircuit) asa percentage ofsupply voltage Max TLC555C 66.7% TLC555I 66.7% TLC555M 66.7% TLC555Q 66.7% Discharge switchon-stage voltage I OL = 10 mA, 25°C TLC555C 0.14 0.5 V TLC555I 0.14 0.5 TLC555M 0.14 0.5 TLC555Q 0.14 0.5 I OL = 10 mA, Full range TLC555C 0.6 V TLC555I 0.6 TLC555M 0.6 TLC555Q 0.6 Discharge switchoff-stage current 25 °C TLC555C 0.1 nA TLC555I 0.1 TLC555M 0.1 TLC555Q 0.1 Max TLC555C 0.5 nA TLC555I 120 TLC555M 120 TLC555Q 120 V OH High-level outputvoltage I OH = –1 µA, 25°C TLC555C 4.1 4.8 V TLC555I 4.1 4.8 TLC555M 4.1 4.8 TLC555Q 4.1 4.8 I OH = –1 µA, Full range TLC555C 4.1 V TLC555I 4.1 TLC555M 4.1 TLC555Q 4.1 V OL Low-level outputvoltage I OL = 8mA, 25°C TLC555C 0.21 0.4 V TLC555I 0.21 0.4 TLC555M 0.21 0.4 TLC555Q 0.21 0.4 I OL = 8mA, Full range TLC555C 0.5 V TLC555I 0.5 TLC555M 0.6 TLC555Q 0.6 10 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Electrical Characteristics: V DD = 5V (continued) over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT (2) These values applyforthe expected operating configurations inwhich THRES isconnected directlytoDISCH ortoTRIG.

V OL Low-level outputvoltage I OL = 5mA, 25°C TLC555C 0.13 0.3 V TLC555I 0.13 0.3 TLC555M 0.13 0.3 TLC555Q 0.13 0.3 I OL = 5mA, Full range TLC555C 0.4 V TLC555I 0.4 TLC555M 0.45 TLC555Q 0.45 I OL = 3.2 mA, 25°C TLC555C 0.08 0.3 V TLC555I 0.08 0.3 TLC555M 0.8 0.3 TLC555Q 0.8 0.3 I OL = 3.2 mA, Full range TLC555C 0.35 V TLC555I 0.35 TLC555M 0.4 TLC555Q 0.4 I DD Supply current(2) 25 °C TLC555C 170 350 µ A TLC555I 170 350 TLC555M 170 350 TLC555Q 170 350 Full range TLC555C 500 µ A TLC555I 600 TLC555M 700 TLC555Q 700 11 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated (1) Fullrange is0°C to 70°C for TLC555C, −40 °C to 85°C for TLC555I, −40 °C to 125 °C for the TLC555Q, and−55 °C to 125 °C for TLC555M.

Forconditions shownasMax ,use theappropriate valuespecified inthe Recommended OperatingConditions table.

7.6 Electrical Characteristics: V DD = 15 V over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT V IT Threshold voltage 25 °C TLC555C 9.45 10 10.55 V TLC555I 9.45 10 10.55 TLC555M 9.45 10 10.55 TLC555Q 9.45 10 10.55 Full range TLC555C 9.35 10.65 V TLC555I 9.35 10.65 TLC555M 9.35 10.65 TLC555Q 9.35 10.65 I IT Threshold current 25 °C TLC555C 10 pA TLC555I 10 TLC555M 10 TLC555Q 10 Max TLC555C 75 pA TLC555I 150 TLC555M 5000 TLC555Q 5000 V I(TRIG) Trigger voltage 25 °C TLC555C 4.65 5 5.35 V TLC555I 4.65 5 5.35 TLC555M 4.65 5 5.35 TLC555Q 4.65 5 5.35 Full range TLC555C 4.55 5.45 V TLC555I 4.55 5.45 TLC555M 4.55 5.45 TLC555Q 4.55 5.45 I I(TRIG) Trigger current 25 °C TLC555C 10 pA TLC555I 10 TLC555M 10 TLC555Q 10 Max TLC555C 75 pA TLC555I 150 TLC555M 5000 TLC555Q 5000 V I(RESET) Reset voltage 25 °C TLC555C 0.4 1.1 1.5 V TLC555I 0.4 1.1 1.5 TLC555M 0.4 1.1 1.5 TLC555Q 0.4 1.1 1.5 Full range TLC555C 0.3 1.8 V TLC555I 0.3 1.8 TLC555M 0.3 1.8 TLC555Q 0.3 1.8 I I(RESET) Reset current 25 °C TLC555C 10 pA TLC555I 10 TLC555M 10 TLC555Q 10 Max TLC555C 75 pA TLC555I 150 TLC555M 5000 TLC555Q 5000 12 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Electrical Characteristics: V DD = 15 V(continued) over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Control voltage (opencircuit) asa percentage ofsupply voltage Max TLC555C 66.7% TLC555I 66.7% TLC555M 66.7% TLC555Q 66.7% Discharge switchon-stage voltage I OL = 100 mA, 25°C TLC555C 0.77 1.7 V TLC555I 0.77 1.7 TLC555M 0.77 1.7 TLC555Q 0.77 1.7 I OL = 100 mA, Full range TLC555C 1.8 V TLC555I 1.8 TLC555M 1.8 TLC555Q 1.8 Discharge switchoff-stage current 25 °C TLC555C 0.1 nA TLC555I 0.1 TLC555M 0.1 TLC555Q 0.1 Max TLC555C 0.5 nA TLC555I 120 TLC555M 120 TLC555Q 120 V OH High-level outputvoltage I OH = –10 mA, 25°C TLC555C 12.5 14.2 V TLC555I 12.5 14.2 TLC555M 12.5 14.2 TLC555Q 12.5 14.2 I OH = –10 mA, Full range TLC555C 12.5 V TLC555I 12.5 TLC555M 12.5 TLC555Q 12.5 I OH = –5 mA, 25°C TLC555C 13.5 14.6 V TLC555I 13.5 14.6 TLC555M 13.5 14.6 TLC555Q 13.5 14.6 I OH = –5 mA, Full range TLC555C 13.5 V TLC555I 13.5 TLC555M 13.5 TLC555Q 13.5 I OH = –1 mA, 25°C TLC555C 14.2 14.9 V TLC555I 14.2 14.9 TLC555M 14.2 14.9 TLC555Q 14.2 14.9 I OH = –1 mA, Full range TLC555C 14.2 V TLC555I 14.2 TLC555M 14.2 TLC555Q 14.2 13 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Electrical Characteristics: V DD = 15 V(continued) over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT (2) These values applyforthe expected operating configurations inwhich THRES isconnected directlytoDISCH orTRIG.

V OL Low-level outputvoltage I OL = 100 mA, 25°C TLC555C 1.28 3.2 V TLC555I 1.28 3.2 TLC555M 1.28 3.2 TLC555Q 1.28 3.2 I OL = 100 mA, Full range TLC555C 3.6 V TLC555I 3.7 TLC555M 3.8 TLC555Q 3.8 I OL = 50 mA, 25°C TLC555C 0.63 1 V TLC555I 0.63 1 TLC555M 0.63 1 TLC555Q 0.63 1 I OL = 50 mA, Full range TLC555C 1.3 V TLC555I 1.4 TLC555M 1.5 TLC555Q 1.5 I OL = 10 mA, 25°C TLC555C 0.12 0.3 V TLC555I 0.12 0.3 TLC555M 0.12 0.3 TLC555Q 0.12 0.3 I OL = 10 mA, Full range TLC555C 0.4 V TLC555I 0.4 TLC555M 0.45 TLC555Q 0.45 I DD Supply current(2) 25 °C TLC555C 360 600 µ A TLC555I 360 600 TLC555M 360 600 TLC555Q 360 600 Full range TLC555C 800 µ A TLC555I 900 TLC555M 1000 TLC555Q 1000 14 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated (1) These values applyforthe expected operating configurations inwhich THRES isconnected directlytoDISCH orTRIG.

7.7 Electrical Characteristics: V DD = 5V At T A = 25 °C, over operating free-airtemperature range(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V IT Threshold voltage 2.8 3.3 3.8 V I IT Threshold current 10 pA V I(TRIG) Trigger voltage 1.36 1.66 1.96 V I I(TRIG) Trigger current 10 pA V I(RESET) Reset voltage 0.4 1.1 1.5 V I I(RESET) Reset current 10 pA Control voltage(opencircuit) asa percentage ofsupply voltage 66.7% Discharge switchon-stage voltage I OL = 10 mA 0.14 0.5 v Discharge switchoff-stage current 0.1 nA V OH High-level outputvoltage I OH = –1 mA 4.1 4.8 V V OL Low-level outputvoltage I OL = 8mA 0.21 0.4 V I OL = 5mA 0.13 0.3 V I OL = 3.2 mA 0.08 0.3 V I DD Supply current(1) 170 350 µ A 7.8 Typical Characteristics Figure 1.Discharge SwitchON-State Resistance vs Free-Air Temperature (1) The effects ofthe load resistance onthese values mustbe taken intoaccount separately.

Figure 2.Propagation DelayTimes toDischarge Output from Trigger andThreshold ShortedTogether vs Supply Voltage 75 50 25 0 25 50 75 100 125 1 2 4 7 10 20 40 70 100 Discharge Switch On-State Resistance ( ) Temperature ( C) V = 15 V, I = 100 mA DD OV = 5 V, I = 10 mA DD O V = 2 V, I = 1 mA DD O 600 500400 300 200 1000 0 2 4 6 8 10 12 14 16 18 20 Supply Voltage (V) Propagation Delay Times (ns) tPLH (1) t PHL I 1 mA C 0 T = 25 C O(on) L A 15 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The TLC555 isaprecision timingdevice usedforgeneral-purpose timingapplications upto2.1 MHz.

8.2 Functional BlockDiagram Pin numbers areforallpackages excepttheFKpackage. RESETcanoverride TRIG,whichcanoverride THRES.

8.3 Feature Description 8.3.1 Monostable Operation For monostable operation,anyofthese timers canbeconnected asshown inFigure 3. If the output islow, application ofanegative-going pulsetothe trigger (TRIG) setstheflip-flop (Q goes low),drives theoutput high, and turns offQ1. Capacitor Cthen ischarged throughR A until thevoltage acrossthecapacitor reachesthe threshold voltageofthe threshold (THRES)input.IfTRIG hasreturned toahigh level, theoutput ofthe threshold comparator resetstheflip-flop (Q goes high), drives theoutput low,anddischarges Cthrough Q1.R1 R S1 THRES R R R TRIG 2 1 GND DISCH 7 3 OUT 6 V DD 8 5 CONT RESET 4 Copyright © 2016, Texas Instruments Incorporated 16 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Feature Description (continued) Figure 3.Circuit forMonostable Operation Monostable operationisinitiated whenTRIGvoltage fallsbelow thetrigger threshold. Onceinitiated, the sequence endsonlyifTRIG ishigh foratleast 10µs before theend ofthe timing interval. Whenthetrigger is grounded, thecomparator storagetimecanbeaslong as10 µs, which limitstheminimum monostable pulse width to10 µs. Because ofthe threshold levelandsaturation voltageofQ1, theoutput pulseduration is approximately t w = 1.1R AC.

Figure 4is aplot ofthe time constant forvarious valuesofR A and C.The threshold levels andcharge ratesbotharedirectly proportional tothe supply voltage, V CC .

The timing interval is,therefore, independent ofthe supply voltage, solong asthe supply voltage isconstant duringthetime interval.

Applying anegative-going triggerpulsesimultaneously toRESET andTRIG during thetiming interval discharges C and reinitiates thecycle, commencing onthe positive edgeofthe reset pulse. Theoutput isheld lowaslong as the reset pulse islow. Toprevent falsetriggering, whenRESET isnot used itmust beconnected toV CC .

Figure 4.Typical Monostable Waveforms Figure 5.Output PulseDuration vsCapacitance Output Pulse Duration s C Capacitance F 10 1 10 1 10 2 10 3 10 4 100 10 1 0.1 0.01 10 5 0.001 t w R A = 10 M R A = 10 k R A = 1 k R A = 100 k R A = 1 M Voltage 2 V/div Time 0.1 ms/div Capacitor Voltage Output VoltageInput Voltage R A = 9.1 k C L = 0.01 F R L = 1 k See Figure 9 VDD ( 5 V t o 1 5 V) R A RL Output GND OUT V DD CONT RESET DISCH THRES TRIG Input 5 8 4 7 6 2 3 1 Copyright © 2016, Texas Instruments Incorporated 17 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Feature Description (continued) 8.3.2 Astable Operation As shown inFigure 6, adding asecond resistor, R B, to the circuit ofFigure 3and connecting thetrigger inputto the threshold inputcauses thetimer toself-trigger andrunasamulti-vibrator. Thecapacitor Ccharges through R A and R B and then discharges throughR B only.

Therefore, theduty cycle iscontrolled bythe values ofR A and R B.

This astable connection resultsincapacitor Ccharging anddischarging betweenthethreshold-voltage level ( ≈ 0.67 ×V CC ) and thetrigger-voltage level(≈ 0.33 ×V CC ).

As inthe monostable circuit,charge anddischarge times (and,therefore, thefrequency andduty cycle) areindependent ofthe supply voltage.

Decoupling CONTvoltage toground withacapacitor canimprove operation. Thisshould beevaluated forindividual applications.

Figure 6.Circuit forAstable Operation Figure 7.Typical Astable Waveforms Figure 8.Trigger andThreshold VoltageWaveform Figure 7shows typicalwaveforms generatedduringastable operation. Theoutput high-level durationt H and low- level duration t L can becalculated asfollows:

(1) (2) Other useful relationships areshown below:

(3) H L A B period t t 0.693 R 2R C L B t 0.693 R C H A B t 0.693 R R C VDD 2/3 V DD 1/3 V DD GND t PHL tPLH tc(H) tc(L) Voltage 1 V/div Time 0.5 ms/div tH Capacitor VoltageOutput Voltage t L R A = 5 k R L = 1 k R B = 3 k See Figure 12 C = 0.15 F GNDOUT V DD CONT RESET DISCH THRES TRIG C R B R A Output R L 0.01 F P V DD (5 V to 15 V) (see Note A) NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Open 5 8 4 7 6 2 3 1 Copyright © 2016, Texas Instruments Incorporated 18 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Feature Description (continued) (4) (5) (6) (7) Figure 9.Free-Running Frequency 8.3.3 Frequency Divider By adjusting thelength ofthe timing cycle,thebasic circuit ofFigure 6can bemade tooperate asafrequency divider.

Figure10shows adivide-by-three circuitthatmakes useofthe fact that re-triggering cannotoccurduring the timing cycle.

Figure 10.Divide-by-Three CircuitWaveformsVoltage 2 V/div Time 0.1 ms/div Capacitor Voltage Output VoltageInput Voltage V CC = 5 V R A = 1250 C = 0.02 F See Figure 9 f Free-Running Frequency Hz C Capacitance F 100 k 10 k1 k 100 10 1 100 10 1 0.1 0.01 0.1 0.001 R A + 2 R B= 10 M R A + 2 R B= 1 M R A + 2 R B= 100 k R A + 2 R B= 10 k R A + 2 R B= 1 k L B H A B t R Low -to-high ratio t R R H B H L A B t R Output waveform duty cycle 1 t t R 2R L B H L A B t R Output driver duty cycle t t R 2R A B1.44 frequency R 2R C 19 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated (1) Forconditions shownasMIN orMAX, usetheappropriate valuespecified underElectrical Characteristics: V DD = 5V .

8.4 Device Functional Modes Table 1shows thedevice functional modes.

Table 1.Function Table RESET VOLTAGE (1) TRIGGER VOLTAGE (1) THRESHOLD VOLTAGE (1) OUTPUT DISCHARGE SWITCH < MIN Irrelevant Irrelevant L On > MAX < MIN Irrelevant H Off > MAX > MAX > MAX L On > MAX > MAX < MIN As previously established Figure 11.Equivalent Schematic(EachChannel)THRES CONT DISCH OUT GND COMPONENT COUNT Transistors Resistors 39 5 V DD TRIG RESET Copyright © 2016, Texas Instruments Incorporated 20 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated 9 Application andImplementation NOTE Information inthe following applications sectionsisnot part ofthe TIcomponent specification, andTIdoes notwarrant itsaccuracy orcompleteness. TI’s customers are responsible fordetermining suitabilityofcomponents fortheir purposes. Customers should validate andtesttheir design implementation toconfirm systemfunctionality.

9.1 Application Information The TLC555 timerdevice usesresistor andcapacitor chargingdelaytoprovide aprogrammable timedelay or operating frequency. TheTypical Applications sectionpresents asimplified discussion ofthe design process.

9.2 Typical Applications 9.2.1 Missing-Pulse Detector The circuit shown inFigure 12can beused todetect amissing pulseorabnormally longspacing between consecutive pulsesinatrain ofpulses. Thetiming interval ofthe monostable circuitisre-triggered continuously by the input pulse trainaslong asthe pulse spacing isless than thetiming interval. Alonger pulsespacing, missing pulse,orterminated pulsetrainpermits thetiming interval tobe completed, therebygenerating anoutput pulse asshown inFigure 13.

Figure 12.Circuit forMissing-Pulse Detector 9.2.1.1 DesignRequirements Input fault(missing pulses)mustbeinput high.Aninput stuck lowcannot bedetected becausethetiming capacitor (C)remains discharged.

9.2.1.2 Detailed DesignProcedure Choose R A and Cso that R A× C >[maximum normalinputhightime]. R Limproves V OH , but itis not required for TTL compatibility.VDD (5 V to 15 V) DISCHOUT V DD RESET R L R A A5T3644 C THRES GND CONT TRIG Input 0.01 F P Output 4 8 3 7 6 2 5 1 Copyright © 2016, Texas Instruments Incorporated 21 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Typical Applications (continued) 9.2.1.3 Application Curve Figure 13.Completed TimingWaveforms forMissing-Pulse Detector 9.2.2 Pulse-Width Modulation The operation ofthe timer canbemodified bymodulating theinternal threshold andtrigger voltages, whichis accomplished byapplying anexternal voltage(orcurrent) toCONT. Figure14shows acircuit forpulse-width modulation.

Acontinuous inputpulse traintriggers themonostable circuit,andacontrol signalmodulates the threshold voltage.Figure15shows theresulting outputpulse-width modulation. Whileasine-wave modulation signal isshown, anywave shape couldbeused.

The modulating signalcanbedirect orcapacitively coupledtoCONT. Fordirect coupling, considertheeffects of modulation sourcevoltage andimpedance onthe bias ofthe timer.

Figure 14.Circuit forPulse-Width ModulationTHRES GND C R A R L V DD (5 V to 15 V) Output DISCH OUT V DD RESET TRIG CONT Modulation Input (see Note A) Clock Input NOTE A: The modulating signal can be direct or capacitiv ely coupled to CONT. For direct coupling, the effects of modulatio n source voltage and impedance on the bias of the timer should be considered. 4 8 3 7 6 2 5 1 Copyright © 2016, Texas Instruments Incorporated Time 0.1 ms/div Voltage 2 V/div VDD = 5 V R A = 1 k C = 0.1 F See Figure 15 Capacitor Voltage Output Voltage Input Voltage 22 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Typical Applications (continued) 9.2.2.1 DesignRequirements The clock inputmusthave V OL and V OH levels thatareless than andgreater than1/3V DD , respectively.

Modulation inputcanvary from ground toV DD .

The application mustbetolerant ofanonlinear transferfunction; the relationship betweenmodulation inputandpulse widthisnot linear because thecapacitor chargeisRC based withannegative exponential curve.

9.2.2.2 Detailed DesignProcedure Choose R A and Cso that R A × C =1/4 [clock inputperiod]. R L improves V OH , but itis not required forTTL compatibility.

9.2.2.3 Application Curve Figure 15.Pulse-Width-Modulation Waveforms 9.2.3 Pulse-Position Modulation As shown inFigure 16,any ofthese timers canbeused asapulse-position modulator.Thisapplication modulates thethreshold voltageandthereby thetime delay ofafree-running oscillator.Figure17shows a triangular-wave modulationsignalforsuch acircuit; however, anywave shape couldbeused.Voltage 2 V/div Time 0.5 ms/div Capacitor Voltage Clock Input Voltage RA = 3 k C = 0.02 F R L = 1 k See Figure 18 Modulation Input Voltage Output Voltage 23 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Typical Applications (continued) The modulating signalcanbedirect orcapacitively coupledtoCONT. Fordirect coupling, considertheeffects of modulation sourcevoltage andimpedance onthe bias ofthe timer.

Figure 16.Circuit forPulse-Position ModulationRB Modulation Input (see Note A) CONT TRIG RESET V DD OUT DISCH V DD (5 V to 15 V) RL R A C GND THRES NOTE A: The modulating signal can be direct or capacitiv ely coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. 4 8 3 7 6 2 5 Output Copyright © 2016, Texas Instruments Incorporated 24 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Typical Applications (continued) 9.2.3.1 DesignRequirements Both DC-andAC-coupled modulationinputchanges theupper andlower voltage thresholds forthe timing capacitor.

Bothfrequency andduty cycle varywiththemodulation voltage.

9.2.3.2 Detailed DesignProcedure The nominal outputfrequency andduty cycle canbedetermined usingformulas inAstable Operation .R L improves V OH , but itis not required forTTL compatibility.

9.2.3.3 Application Curve Figure 17.Pulse-Position-Modulation Waveforms 9.2.4 Sequential Timer Many applications, suchascomputers, requiresignalsforinitializing conditions duringstart-up. Other applications, suchastest equipment, requireactivation oftest signals insequence. Thesetimingcircuits canbe connected toprovide suchsequential control.Thetimers canbeused invarious combinations ofastable or monostable circuitconnections, withorwithout modulation, forextremely flexiblewaveform control.Figure18 shows asequencer circuitwithpossible applications inmany systems, andFigure 19shows theoutput waveforms.Voltage 2 V/div RA = 3 k R B = 500 R L = 1 k See Figure 20 Capacitor Voltage Output Voltage Modulation Input Voltage Time 0.1 ms/div 25 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Typical Applications (continued) S closes momentarily att= 0.

Figure 18.Sequential TimerCircuit 9.2.4.1 DesignRequirements The sequential timerapplication chainstogether multiplemonostable timers.Thejoining components arethe 33-k Ωresistors and0.001- µF capacitors. Theoutput hightolow edge passes a10- µs start pulse tothe next monostable.

9.2.4.2 Detailed DesignProcedure The timing resistors andcapacitors canbechosen usingthisformula: t w = 1.1 ×R ×C.S VDD RESET V DD OUT DISCH GND CONT TRIG 4 8 3 7 6 1 5 2 THRESR C C C 0.01 CC = 14.7 F P R C = 100 k :

Output C RESET V DD OUT DISCH GND CONT TRIG 4 8 3 7 6 1 5 2 THRESR B 33 k :

0.001 0.01 P F CB = 4.

7P F R B = 100 k : Output B Output A R A = 100 k :

C A = 10 PF P F 0.01 P F 0.001 33 k :

RA THRES 2 5 16 7 3 8 4 TRIG CONT GNDDISCH OUT V DD RESET P FP F C B C A NOTE A: S closes momentarily at t = 0. Copyright © 2016, Texas Instruments Incorporated 26 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated Typical Applications (continued) 9.2.4.3 Application Curve Figure 19.Sequential TimerWaveforms 10 Power Supply Recommendations The TLC555 requires avoltage supplywithin2V to 15 V.Adequate powersupply bypassing isnecessary to protect associated circuitry.Minimum recommended is0.1- μF ceramic inparallel with1-μF electrolytic. Placethe bypass capacitors asclose aspossible tothe TLC555 andminimize thetrace length.Voltage 5 V/div t Time 1 s/div See Figure 22 Output A Output B Output C t = 0 tw C = 1.1 R CC C tw C t w B = 1.1 R BC B tw A = 1.1 R AC A tw A t w B 27 TLC555 www.ti.com SLFS043H–SEPTEMBER 1983–REVISED AUGUST2016 Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated 11 Layout 11.1 Layout Guidelines Standard PCBrules apply torouting theTLC555. The0.1-μF ceramic capacitor inparallel witha1- μF electrolytic capacitor mustbeasclose aspossible tothe TLC555. Thecapacitor usedforthe time delay mustalsobeplaced as close tothe discharge pin.Aground planeonthe bottom layercanbeused toprovide betternoiseimmunity and signal integrity.

Figure 20isthe basic layout forvarious applications.

• C1—based ontime delay calculations • C2—0.01- μF bypass capacitor forcontrol voltage pin • C3—0.1- μF bypass ceramic capacitor • C4—1-μF electrolytic bypasscapacitor • R1—based ontime-delay calculations 11.2 Layout Example Figure 20.Layout Example GND TRIG OUT RESET VDD DISCH THRES CONT TLC555 C4 C3R1 C1 C2 28 TLC555 SLFS043H –SEPTEMBER 1983–REVISED AUGUST2016 www.ti.com Product FolderLinks:TLC555 Submit Documentation Feedback Copyright ©1983 –2016, Texas Instruments Incorporated 12 Device andDocumentation Support 12.1 Receiving Notification ofDocumentation Updates To receive notification ofdocumentation updates,navigatetothe device product folderonti.com. Inthe upper right corner, clickonAlert metoregister andreceive aweekly digestofany product information thathas changed.

Forchange details,reviewtherevision historyincluded inany revised document.

12.2 Community Resources The following linksconnect toTI community resources.Linkedcontents areprovided "ASIS"bythe respective contributors.

Theydonot constitute TIspecifications anddonot necessarily reflectTI'sviews; seeTI'sTerms of Use .

TI E2E ™Online Community TI'sEngineer-to-Engineer (E2E)Community. Createdtofoster collaboration among engineers. Ate2e.ti.com, youcanaskquestions, shareknowledge, exploreideasandhelp solve problems withfellow engineers.

Design Support TI'sDesign Support Quicklyfindhelpful E2Eforums alongwithdesign support toolsand contact information fortechnical support.

12.3 Trademarks LinCMOS, E2Earetrademarks ofTexas Instruments.

All other trademarks aretheproperty oftheir respective owners.

12.4 Electrostatic DischargeCaution These devices havelimited built-in ESDprotection. Theleads should beshorted together orthe device placed inconductive foam during storage orhandling toprevent electrostatic damagetothe MOS gates.

12.5 Glossary SLYZ022 —TIGlossary .

This glossary listsandexplains terms,acronyms, anddefinitions.

13 Mechanical, Packaging,andOrderable Information The following pagesinclude mechanical, packaging,andorderable information. Thisinformation isthe most current dataavailable forthe designated devices.Thisdata issubject tochange withoutnoticeandrevision of this document. Forbrowser-based versionsofthis data sheet, refertothe left-hand navigation. PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package TypePackageDrawingPinsPackageQtyEco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLC555CD ACTIVE SOICD875Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70TL555C TLC555CDG4 ACTIVE SOICD875Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70TL555C TLC555CDR ACTIVE SOICD82500Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70TL555C TLC555CDRG4 ACTIVE SOICD82500Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70TL555C TLC555CP ACTIVE PDIPP850Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type0 to 70TLC555CP TLC555CPE4 ACTIVE PDIPP850Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type0 to 70TLC555CP TLC555CPSR ACTIVE SOPS82000Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70P555 TLC555CPW ACTIVETSSOPPW1490Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70P555 TLC555CPWR ACTIVETSSOPPW142000Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70P555TLC555CPWRG4 ACTIVETSSOPPW142000Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70P555 TLC555ID ACTIVE SOICD875Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM-40 to 85TL555I TLC555IDG4 ACTIVE SOICD875Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM-40 to 85TL555I TLC555IDR ACTIVE SOICD82500Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM-40 to 85TL555I TLC555IDRG4 ACTIVE SOICD82500Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM-40 to 85TL555I TLC555IP ACTIVE PDIPP850Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type-40 to 85TLC555IP TLC555IPE4 ACTIVE PDIPP850Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type-40 to 85TLC555IP TLC555QDR ACTIVE SOICD82500Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM-40 to 125TL555Q PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2016 Addendum-Page 2 Orderable Device Status (1) Package TypePackageDrawingPinsPackageQtyEco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLC555QDRG4 ACTIVE SOICD82500Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL555Q (1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

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Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC555 : PACKAGE OPTION ADDENDUM www.ti.com 2-Feb-2016 Addendum-Page 3 •Automotive: TLC555-Q1 •Military: TLC555M NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Military - QML certified for Military and Defense Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device PackageType PackageDrawing Pins SPQ ReelDiameter(mm) ReelWidthW1 (mm) A0(mm) B0(mm) K0(mm) P1(mm) W(mm) Pin1Quadrant TLC555CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC555CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLC555IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC555QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC555QDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC555CDR SOIC D 8 2500 340.5 338.1 20.6 TLC555CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLC555IDR SOIC D 8 2500 340.5 338.1 20.6 TLC555QDR SOIC D 8 2500 367.0 367.0 38.0 TLC555QDRG4 SOIC D 8 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated anditssubsidiaries (TI)reserve theright tomake corrections, enhancements, improvementsandother changes toits semiconductor productsandservices perJESD46, latestissue, andtodiscontinue anyproduct orservice perJESD48, latest issue.

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