8. Assume a non-pipelined processor design has a cycle time of lns. a. [3] What is the best speedup you can get by pipelining it into 5 stages? b.

Assume a non-pipelined processor design has a cycle time of 10ns

8. Assume a non-pipelined processor design has a cycle time of lflns.a. [3] What is the best speedup you can get by pipelining it into 5 stages? b. [3] If the 5 stages are 111s. 1.5 ns, 4 ns, 3ns and 0.5ns. What is the speedup youcan get compared to the original processor? c. [4] If each pipeline stage also adds 20ps due to register setup delay, what is thebest speedup you can get compared to the original processor? 9. The pipeline in 8c) above stalls 20% of the time for 1 cycle and 5% of the time for 2cycles (these occurrences are disjoint. The average CPI of the non-pipelined processor is 1.4. a. [3] What is the new CPI?b. [3] What is the Speedup?