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A digital logic circuit is vulnerable to hardware faults at different test points. Suppose there are total N test points of which K ( N ) are faulty....
Q. A digital logic circuit is vulnerable to hardware faults at different test points. Suppose there are total N test points of which K (≤ N) are faulty.
a. If an engineer selects n (≤ N) distinct points for testing. What is the probability that k (≤ n) are faulty points. Begin by defining X be random variable whose value equals number of k faults out of n test points.
b. In Very Large Scale Integration (VLSI) the circuit size (therefore N) can be extremely large. Show how does the random variable X defined in (a) converge to a famous discrete random variable with parameters (n, p, k) where p = K/N.
c. In modern VLSI circuits, the technological advancements render hardware faults very rare. Consequently, the average number of faults w in an N-test points VLSI
circuit can be considered constant. Under this assumption, show that in the circuit, that number of fault points designated by the random variable Z, converge from Y
in (b) to Poisson random variable with w = K . Write down an expression for P(Z> k) in terms of k and w .
d. Intel has developed an automatic system for testing hardware faults. The system spends t ms scanning a test point. If the last fault point was detected 1 ms ago,
what is the probability that next fault point will be identified before 2 ms?
