Consider a modified dynamic logie shown in Figure 2 . This logic style is called the DOMINO LOGIC since dynamic logic gates cannot be cascaded...

Consider a modified dynamic logic shown in Figure.

Consider a modified " dynamic logie shown in Figure 2 . This logic style is calledthe DOMINO LOGIC since dynamic logic gates cannot be cascaded directlyTherefore , inserting inverters between the various stages of dynamic logic isrequired1 4D -PulldownPulldownPulldowOutOutQUIZOut 3PulldownNetworkNetworkNetworkNetwor-Q ---Figure 2 : Cascaded dynamic logic gates using static CMOS inverters . This logicstyle is called Domino logic .Assume that the PDN in each dynamic gate is a single MOS device . Assumehat ththat the time to pro- charge and evaluate is equal to I 2 Also the propagationtiondelay of the static CMOS inverter is also equal to I / 2 . Also the clock & has aperiod of LOTAssuming that the clock has a 50% duty cycle , show the timing diagramfor one clock period starting at $ = 0 for the clock ( ) , Out , Out 2 , Out ?Outand Out . Assume that IN is HIGH for the entire periodb . Assume that you can design an unbalanced static CMOS inverter withlow - to high propagation delay Tech and high-to low propagation delayIPAL . Find the largest values of Tony and Iput that guarantee thatOut4 would have reached its correct value by the end of the clock periodfor both IN - 1 and IN - O ( you can assume , as before , that IN remainsIN remainconstant at either I or O throughout the entire clock period )Note that the pre - charge and evalaute phases each last for 1 / 2 clock period . Here I / 2denotes the delay to pre- charge and the delay to evaluate the resul