Create a structural description of the following logic equations. Simplify the logic equations so that you use a minimum number of 2-input AND...

1. Create a structural description of the following logic equations. Simplify the logic

equations so that you use a minimum number of 2-input AND gates, 2-input OR gates,

and inverters. Give each gate a delay of 1 time unit. Use ModelSim to simulate your

design for all possible input combinations. Turn in your Verilog code and ModelSim

simulation results for your design, along with a schematic that shows how your design is

implemented. How many of each type of gate does your design use?

Z ABC AD BD ABC

Y BD ABC ACD ABC ACD

   

    

2. Draw the schematic of a transparent latch, popularly known as a D- latch. This design is

to be transferred into Verilog while maintaining signal names and gate types.

a) First convert the transparent latch to STRUCTURAL Verilog. (HINT: This requires

the use of primitives and wires.)

b) Now code a RTL Verilog description of the transparent latch. (HINT: Continuous

assignment statements should be used.)

c) Which style Verilog, structural or RTL, is easier to work with? Why?

3. Examine the following set of circuits, some of which are faulty. Each circuit is suppose to

implement combinational logic that performs f = (x ^ y) | z. Do NOT have to turn in .v

files for these four circuits.

module circuit1(output reg f, input x, y, z);

wire temp = x ^ y;

always @(temp, z) f = temp | z;

endmodule

module circuit2(output reg f, input x, y, z);

reg temp;

always @(x,y,z) begin

temp <= x ^ y;

f <= temp | z;

end

endmodule

module circuit3(output reg f, input x, y, z);

reg temp;

always @(y,z) begin

temp = x ^ y;

f = temp | z;

end

module

module circuit4(output f, input x, y, z);

reg temp;

always @(x,y,z) begin

temp = x ^ y;

f = temp | z;

end

endmodule

(a) Write a testbench instantiating all four circuits and sending the same input to each. Use a for-loop to generate the x, y, and z input values, and instead of looping 8 times, loop 10 times. For the simulation waveform, show x, y, and z, and the f values (labled as f1 to f4). Which of these are incorrect? For each incorrect circuit, indicate why it is incorrect and what that effect has on simulation.

(b) Synthesize the circuits above. Indicate which (if any) completely fail to synthesize. For circuits that fail to compile or synthesize correct their errors and synthesize them again. For ones that generate warnings, briefly summarize the warnings seen.

4. A Verilog description of a full adder and its corresponding testbench are provided

below.

Testbench Code

module tfull_adder_3b (A, B, c_in);

input [2:0] A, B;

input c_in;

output [2:0] sum;

output c_out;

reg clk;

reg [5:0] count;

full_adder (A, B, c_in, sum, c_out);

initial

$monitor($time, “ A=%h B=%h c_in=%b sum=%h c_out=%b”,

A, B, c_out, sum, c_in);

initial begin

clk = 0; count = 4’b0;

#100 $stop

end

always

#5 clk != clk;

always@(posedge clk)

count = count++;

assign A = count[7:4];

assign B = count[3:1];

assign c_in = count[1];

endmodule

Verilog Description

module full_adder_3b (sum, c_out, A, B, c_in);

input [2:0] A, B;

input c_in;

output [2:0] sum;

output c_out;

assign {c_out, sum} = {1’b0,A} + B + c_in;

endmodule

a) Rewrite the testbench so it both compiles and fully simulates the 3-bit full adder for all binary input combinations. In addition, connect ports by name, instead of order. Submit your revised code and simulation results.

b) Rewrite the 3-bit full adder as a hierarchical design, which calls two 3-bit, RTL half adders. Submit your debugged code.

c) Simulate both adder designs and use ModelSim’s Waveform Comparison feature to verify that the original full adder and the one from part B are functionally equivalent. Submit the results of the waveform comparison.

Comment 1: Make sure signal labels only display the signal’s name and not the hierarchical path in front of the name. To do this, go to ModelSim’s Main window and open up the Preferences window under Tool > Edit >Preferences. In the By Name tab, expand Wave and set signalNameWidth to 1. Save your changes.

Comment 2: In addition, adhere to good annotation technique and divide the waveforms into single input combination periods with vertical lines.

5. You are to design and test a priority encoder for an interrupt system. There are six interrupt lines. The encoder is to output the 3-bit code that corresponds to the highest numbered interrupt line with a 1 value on it. If all I lines are 0, the encoder is to output 000. The behavior is described by the compact truth table below. All rows not represented in the truth table have don’t care output values.

a) Write a Verilog module for the priority encoder using one or more continuous assignment statements. Make Interrupt Lines and Interrupt Code vectors (multibit), not to be confused with vectored vs. scalared Verilog variables. Submit your debugged code.

b) Write a Verilog module for the priority encoder using an always behavior. Submit your debugged code.

c) Write a testbench which instantiates your two modules, applies the vectors given in the above truth table to the two circuits, and compares their outputs using the === Verilog operation on the two C vectors to produce an output good that is 1 if they match. Simulate your designs and provide a printout of the waveforms to verify your designs and to show that they have identical functionality. Submit testbench code and annotated simulation results.

Comment: Display vector signals in binary in unexpanded form.

6. For each procedural assignment given below that is labeled with a comment tell when the LHS is evaluated, when the RHS is assigned, and the value assigned to the RHS. Assume there is a single positive clock edge at time 5. A single procedural assignment may be evaluated and assigned more than once. Note: Some of the timing for the above module is tricky, so you may want to simulate the circuit to make sure you understand the timing correctly. You do not have to turn in Verilog files for this problem. Record the evaluations and assignments chronologically using the following format (as an example):

Time = 1: b + d evaluates to 6

Time = 1: t1 is assigned 6

module timing(output reg [4:0] result);

reg [4:0] a = 1, b = 2, c = 3, d = 4, t1, t2;

reg clk;

initial begin clk = 0; #5 clk = 1; end

always @(posedge clk) begin

b <= #1 a+3; // assignment 1

#2 c <= b + a; // assignment 2

d <= #3 c + b; // assignment 3

end

always @(*) begin

# 1 t1 = b + d; // assignment 4

t2 = #2 c + a; // assignment 5

result = #3 t1 + t2; // assignment 6

end

endmodule