CSCI 6643 Operating Systems Fall 2018HW #4 - Memory System DesignDue: November 28, 2018The purpose of this assignment is to design a memory system using a set of potential componentsand algorithms. Th

CSCI 6643 Operating Systems Fall 2018HW #4 - Memory System DesignDue: November 28, 2018The purpose of this assignment is to design a memory system using a set of potential componentsand algorithms. The major design criteria will be the eective access time of the system and theoverall monetary cost of the system. The features of each of the system components are given below.Secondary memory - disk driveA disk will be used as secondary storage. Each potential disk drive will be big enough to holdthe swap space for a virtual memory system of 4GBytes. There are two potential drives to select:Seek time Rotation speed Transfer rate Cost9ms 5400 rpm 60MB/s $1006ms 7200 rpm 100MB/s $150The seek time is the average overhead necessary to nd the particular track containing the datato be transferred, and is the same regardless of the amount of information being transferred. Therotational speed aects the latency necessary to nd the proper sector in a track. Assume that onehalf of a rotation is required on average. The transfer rate is the rate at which data can be read orwritten to the disk after the appropriate sector has been found.Main Memory - RAMThe amount of physical RAM to be used in the system can be chosen from one of three sizes:32MB, 128MB or 1GB. The DRAM can be formed using a set of chips with one of two dierentcharacteristics:Access time Cost60ns $60 for every 32MB50ns $80 for every 32MBThe access time is the time taken to read or write a single data item to memory. The total costof the memory chips depends on the total size of the RAM chosen.L2 Cache - lower levelThe amount of L2 (external) cache which can be used in the system can be chosen from one ofthree sizes: 64K, 256K or 1M. These sizes refer to the number of data entries in the cache. Twodierent chips with dierent characteristics can be chosen:Access time Cost15ns $8 for every 64K entries10ns $11 for every 64K entriesThe access time is the time taken to read a single data entry from the cache. The total cost ofthe memory chips depends on the size of the cache chosen.L1 Cache - upper levelThe amount of L1 (on chip) cache which can be used in the system can be chosen from oneof three sizes: 1K, 4K or 32K. These sizes refer to the number of data entries in the cache. Twodierent chip characteristics can be chosen:Access time Cost2ns $10 for every 1K entries1ns $15 for every 1K entriesThe access time is the time taken to read a single data entry from the cache. The total cost ofthe cache depends on the size of the cache chosen.RAM - Disk interfaceYou are implementing a virtual memory of size 4GB. The three possible page sizes that you canchoose from are : 1KB, 4KB and 16KB. This choice will aect the page transfer times, the numberof frames in the RAM, and the RAM hit rate.The management of the placement of pages in the RAM and their replacement, will be governedby one of two strategies: FIFO or LRU. The miss rates for the FIFO strategy depend on the sizeof physical RAM, namely (32MB - 0.001%, 128MB - 0.0001%, and 1GB - 0.00001%). If the LRUstrategy is used, the miss rates decrease by 20%. However, the tradeo is a time overhead to dothe bookkeeping. The increase in access time for a miss is 0.01ns per frame in the RAM (size ofRAM divided by number of pages). The page size also aects the miss rate. The above values areused for 1KB size pages. For 4KB pages the miss rates are reduced by 5%, and for 16KB pages themiss rates are reduced by 10%. Whenever a page must be replaced, assume that 25% of the timethe page to be replaced is dirty and must be written back to the disk, before the new page can beloaded in, and a nal RAM access can be made.L2 Cache - RAM interfaceThe management of the placement of data in the external L2 cache and its replacement willbe governed as follows. The mapping will be either fully associative or 2-way set associative. Andeither random or LRU replacement will be used. The miss rates for these strategies, given thedierent cache sizes are:Cache size 2-way Random Full Random 2-way LRU Full LRU64K entries 1.35% 1.2% 1.25% 1.1%256K entries 1.02% 0.91% 1.0% 0.9%1M entries 0.66% 0.6% 0.65% 0.6%While the LRU and Fully associative strategies provide better miss rates, they have a price. Inorder to perform fully associative mapping additional hardware is needed that increases the costof the cache by 10%. To use the LRU algorithm requires a time overhead per access of 10