For a direct mapped design with a 32-bit address the following bits if the address is used to access the cache: a. What is the cache line size (in

For a direct mapped design with a 32-bit address the following bits if the address is

used to access the cache:

a. What is the cache line size (in words)?

b. How many entries does the cache have?

c. What is the ratio between total bits (ignore valid bits) required for such a

cache implementation over the data storage bit?