I am trying to determine the minimum and maximum propagation delays for combinational logic blocks.

There are 2 combinational logic blocks and 3 registers (register>logic1>register>logic2>register)

For the following synchronous circuit the registers have:

t-setup=10ps

t-hold=-5ps

t-chqv=20ps

-300ps<delay1<300ps

-100ps<delay2<300ps

-300ps<delay3<200ps

The clock is a spread spectrum with a nominal value of 200MHz and a variation of plus or minus 1%.

i) Determine the minimum and maximum propagation delays for combinational logic block 1 (Comb Logic1) and combinational logic block 2 (Comb Logic2). Show how you calculate this.

ii) If combinational logic block 1 has a minimum delay of 580ps and a maximum delay of 600ps and combination logic block 2 has a minimum delay of 500ps and a maximum delay of 700ps how large could the clock delay to register bank 3 (i.e. the far right register bank) become and the circuit still operate correctly (note: register banks 1 and 2 still have delays between -300ps and +300ps and -100ps and +300ps respectively)? Show how you calculate this.

iii) If both combinational blocks have a minimum delay of 600ps and a maximum delay of 800ps how large could the nominal clock frequency become (assume clock variation is still +/- 1%) and the circuit still operate correctly (note: all register banks have clock delay as per the diagram)? Show how you calculate this