It is required to design a circuit that receives a 4bit signed numbers in 2's complement representation A=AgAlAg and produces a 7bit ouggnt C=...

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Show the block diagram design of your circuit 

Model your design in Verilog by modeling each component separately 

It is required to design a circuit that receives a 4—bit signed numbers in 2‘s complementrepresentation A=§AgAlAg and produces a 7—bit ouggnt C= C5C5C4C3C2C1Cu. Thecircuit implements the following fisnctions based on the values of the three selectioninputs: S], 51 and SD. + 32 51 SO Function0 O O C=3A01 C=3A+110 C=4All C=4A+lO O C=5A011011 C=5A+1C=6A |C=6A+1 0001111 a) (15 points) Show the block diagram design of your circuit using MSI componentslike Adder, Multiplexor, as needed. Use only one adder in your solution. b) (15 points) Model your design in Verilog by modeling each component separately i.e.adder, MUX, etc. and then instantiating these components to model your circuit.Each component can be modeled using behavioral model.