Let's say that you have a logic gate of y=(a,b)=a' + b With wave generator and a logic analyzer, Select test signals (waveforms) for inputs a and b

Let's say that you have a logic gate of y=(a,b)=a' + b

With wave generator and a logic analyzer,

Select test signals (waveforms) for inputs a and b suitable for determination of the circuit propagation delay in order to avoid the possibility of appearance of glitches at the output. you can exclude racing of signals at the inputs of OR2 gate.

could you please provide me a square - waveform graph from 0ns to 250 ns for a, b and y with circuit propagation delay with 95ns?