M7A3 Lab: Counters and Seven-Segment Display ObjectivesThe objectives of this experiment are to:• Examine binary and BCD counter packages. • Cascade multiple counters for large counting sequences.

M7A3 Lab: Counters and Seven-Segment Display Objectives

The objectives of this experiment are to:

• Examine binary and BCD counter packages. • Cascade multiple counters for large counting sequences. • Examine seven-segment displays

Introduction

In this experiment we examine several standard counting and display packages. The devices are used for both binary and BCD (binary coded decimal) counting and display. BCD counters are also called decade counters, since they only count from 0 to 9.

We will also see how multiple counters are cascaded to make larger counters, such as two 4-bit counters making an 8-bit counter. We will also display the count using seven-segment displays.

Procedure

1. Load the circuit E7A-1.MS7, shown in Figure 7A.1.

Figure 7A.1: 7490 decade counter

The 7490 decade counter is wired internally to reset from nine back to zero. Verify that the counting sequence goes from zero to nine.

2. What happens if both R0 inputs are pulled high while the 7490 is counting? Demonstrate this in the circuit.

3. What happens if both R9 inputs are pulled high during counting?

4. What happens if the B-CLK input is disconnected from the A output during counting? 5. View the counting sequence using the logic analyzer.

6. Load the circuit E7A-2.MS7, shown in Figure 7A.2.

Figure 7A.2: 7493 4-bit binary counter 7. Simulate the circuit. There should be 16 different output patterns.

8. Use either circuit (7490 or 7493) to make a modulo-6 counter. This is done by connecting the B and C outputs back to the R0 inputs. Be sure to disconnect the ground from each R0 input first.

9. Use the 7493 to make a modulo-11 counter. Note: additional circuitry is required to make this possible.

10. Load the circuit E7A-3.MS7, shown in Figure 7A.3.

Figure 7A.3: Cascaded decade counters

11. Use the Logic Analyzer to verify that there are 100 different output patterns. The A output on the first 7490 is the LSB. The D output on the second 7490 is the MSB.

12. If the input frequency is set to 1 kHz, what is the frequency on each of the eight outputs?

Output FREQ OUTPUT Freq

A1 (LSB) A2

B1 B2

C1 C2

D1 D2 (MSB)

Table 7A.1: Output frequencies for cascaded 7490’s

13. Repeat steps 11 and 12 for two cascaded 7493 counters. How many output patterns are there? What are the frequencies at each output?

Output FREQ OUTPUT Freq

A1 (LSB) A2

B1 B2

C1 C2

D1 D2 (MSB)

Table 7A.2: Output frequencies for cascaded 7493’s

14. Use two 7490’s or two 7493’s to make a modulo-87 counter.

15. Modify the circuit E7A-1.MS7 so that the count is displayed in a common anode seven- segment display. Verify that the count goes from 0 to 9.

16. Repeat step 15 with a common cathode seven segment display.

Discussion

While reviewing your data and results, provide detailed answers to each of the following:

1. What clock edge is required by the 7490 and 7493? 2. How many 7490’s are required to make a modulo-320 counter? How many 7493’s? 3. Why is it proper to use the D output (the MSB) as the clock to the next counter when

cascading counters? 4. Are the 7490 and 7493 counters pin compatible? 5. Are common-anode and common-cathode seven-segment displays compatible?