Since a nop instruction is implemented as sll $0,$0,0 and register $0 can't be written (i.

Since a nop instruction is implemented as   sll  $0,$0,0  and register $0 can’t be written (i.e., it is read only),  can the nop instruction ever take more than 5 cycles to go through our 5-stage MIPS pipeline? Explain your answer.