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Some processor use block transfer instructions to move multiple words from-to IO devices. If a processor uses this IO instruction to move 256 bytes...
Q1. Some processor use block transfer instructions to move multiple words from-to IO devices. If a processor uses this IO instruction to move 256 bytes and it will take 4 clock cycles per byte moved. In addition, if the processor needs 15 clock cycles in non-block instruction then calculate the increase in speed compared to non-blocking instruction?
Q.2 If we have a processor connected to 50 Hz clock timer to help in scanning an IO device with that frequency. The processor reads a status register to check the time in one instruction, check the status bit in 2 instructions and finally execute the IO movement in one instruction likewise. How long it takes to check and output to the device for 1 byte if processor clock rate is 5 MHz and if you know that each instruction takes in average 4 CLK cycles to execute?
Q.3 If we have a processor connected to an IO device for data movement by a rate of 10 KBPS. Assume an interrupt driven strategy is applied here. Assume when interrupt occurs until service is done will be takes 80 us. If it interrupts for one byte every time then what is the fraction of time consumed (fraction between servicing and total time)?
Q.4 A DMA module is transferring data to a memory using cycle stealing from the device that transmit data at a rate of 20 KBPS. Frequency of the CPU is 2.5 MIPS. By how much the DMA module will slow down the CPU if it steals 2 cycles for every byte moved to IO?
Q.5 For the 8237 the DMA chip module, if a block transfer takes 2 clock cycles per DMA cycle in which one byte is transferred every time. Suppose that the clock frequency is 4 MHz then what will be the maximum transfer rate that this module
