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The CPU within a computer system employs a split cache system in which the separate instruction and data caches are fully associative.
4. The CPU within a computer system employs a split cache system in which the separate instruction and data caches are fully associative. A program runs on this system and writes to a memory mapped register that triggers an I/O device to begin writing a 32-bit value directly into memory at address 0x04CA0000 using DMA and bypassing the cache. The value first written by the device is 0x00001234 and every second thereafter the I/O device writes a new value (= old value + 1) to the same location. Assume that address 0x04CA0000 and the memory mapped device register are the only two data items referenced in memory.
After triggering the I/O device to start writing, the program enters a loop in which it reads the contents of the word at address 0x04CA0000. The loop is repeated once every 5 seconds thereafter. If the first value read within the loop is 0x00001234, what value would be read 35 seconds later?
