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To implement a chip that should provide the following functionality: (maximum of 2 marks each, one for successful implementation, one for...
Can someone help me improving my nand2teris hdl code for this question?
// if (nx == 1) set x = !x // bitwise not
// if (zy == 1) set y = 0 // 16-bit constant
// if (ny == 1) set y = !y // bitwise not
// if (no == 1) set out = !out // bitwise not
// if (cx == 1) set t+1 = out //
// if (re == 1) set out = 0
//if (opt ==1) set out = x * y
// if (out == 0) set zr = 1
// if (out < 0) set ng = 1
CHIP ALU {
IN
x[16], y[16], // 16-bit inputs
nx, // negate the x input?
zy, // zero the y input?
ny, // negate the y input?
no; // negate the output?
cx; //x for t+1 = out
re,// reset output =0
opt;// x*y multiply
OUT
out[16], // 16-bit output
zr, // 1 if (out==0), 0 otherwise
ng; // 1 if (out<0), 0 otherwise
of; // 1 if overflows
PARTS:
Mux16(a=x, b=loop, sel=cx, out=cxout);
Not16(in=cxout, out= nx);
Mux16(a=cxout, b=nx, sel=nx, out=x2); // x2 = 0, x, -x
Mux16(a=y, b[0..15]=false, sel=zy, out=y1);
Not16(in = y1, out=ny1);
Mux16(a=y1, b=ny1, sel=ny, out=y2); // y2 = 0, y, -y
Add16(a=x2, b=y2, out=o1);
And16(a=x2, b=y2, out=o1);
Not16(in=o1, out=noto1);
Mux16(a=o1, b=noto1, sel=ny, out=o1);// o1 = x+y, x-y, y-x, 0, -y-x, x, -x, y,-y
Add16(a=o1, b[1..15]=false, b[0]=true, out=o2); // o2 = x+1
Not16(in=o2, out=noto2);
Mux16(a=o1, b=noto1, sel=no, out=o2);
opt16(a=x2, b=y2, out=o3); //o3= x*y
Mux16(a=o1, b=o3,sel=opt, out=o3);
Mux16(a=o3, b=false, sel=re, out=o4);
And16(a=o3, b=true, out=output);
Register(in=ouput , load=true, out=out, out=loop);
}
- Attachment 1
- Attachment 2