21. RISC architectures attempt to improve CPU performance by a) pipelining all their instructions b) reducing the number of sub-steps in the

21. RISC architectures attempt to improve CPU performance bya) pipelining all their instructionsb) reducing the number of sub-steps in the instruction cycle by onec) overcoming manufacturing problemsd) reducing the number of addresses accessible via the MARe) eliminating the two major bottlenecks slowing the CPU