Assume memory accesses take 70 ns and the memory accesses are 36% of all instructions. For a given processor P1, the L1 cache size is 2KB, L1 miss...

Assume memory accesses take 70 ns and the memory accesses are 36% of all instructions. For a given processor P1, the L1 cache size is 2KB, L1 miss rate is 8%

and L1 Hit time is 0.66ns.

a. Assuming that the L1 hit time determines the cycle times for P1, what is the clock rate of P1.

b. What is the AMAT for P1?

c. What is the AMAT for P1 with the addition of an L2 cache? Assume the L2 miss rate is 95% and L2 hit time is 5.62ns.