design a modulo-6 counter, which counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1. the counter counts the clock pulses if its enable input, w, is equal...

design a modulo-6 counter, which counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1.....

the counter counts the clock pulses if its enable input, w, is equal to 1. Use JK flip flops in the circuit.

Please show the state diagram (or state table), state assignment, state-assigned table, excitation table, expressions for next-state logic and output logic, and the circuit diagram of your design.

It’s also known as divide-by-6 counter, it is constructed using three D-type flip-flops. It isdesigned in a manner that that it counts from 1 to 5 and on hitting 6 it resets.Below is the details;