Design a Verilog system that will accept a block of data words encoded as specified in Part 1; then check the parity for each data word and for the...

Design a Verilog system that will accept a block of data words encoded as specified in Part 1; then check the parity for each data word and for the block. The system should output each of the 8-bit data words, issue a word error if the parity is incorrect for any word, and issue a block error if the block check word is in error.