Laboratory 3 Counters Prelab 1) complete all Verilog files 2) compile your designs 3) simulations(optional) Objectives 1) Design counter using...

Laboratory 3 Counters

Prelab

complete all Verilog files

compile your designs

simulations(optional)

Objectives

Design counter using flip-flops.

Design counter using behavior statements.

Design a timer.

Part1               8-bit synchronous counter using T flip-flops and AND gates

Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses four T-type flip-flops. The counter increases its value on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear signal low. You are to implement an 8-bit counter of this type.

Circuit description

Figure 1. 4-bit synchronous counter (but you need to implement 8-bit counter)

            Specific notes:

You should build a T flip-flop module first, and then instantiate 8 times to create the counter.

Use SW[1] for Enable, SW[0] for Clear, KEY[0] for clock.

The output of left TFF is Q[0] (LSB).

The output Q[7:0] should go through 7-seg display so that the output of the 8-bit counter can be display on HEX1 and HEX0.

[prelab: complete the following Verilog files]

T-flipflop design

module tff0(resetn, t, clock, q);

BCD-7-seg design: seg7.v (available from Lab2)

Top-level design

module lab3_part1(SW, KEY, HEX1, HEX0);

            endmodule

Implementation (put a check mark when you finish the step)

______Create a new project.

______Write Verilog files (lab3_part1.v, tff0.v, seg7.v) required by the above description and notes.

______Download DE2_pin_assignments.qsf from altera website.

In Quartus II, select assignments à import assignments, choose DE2_pin_assignments.qsf in the file box.

______Compile your design.

_______Toolsà programmer, download the circuit into FPGA, and test the functionality.

_______Using Quartus II, find out how many logic elements (LEs) are used to implement your circuit.

_______Using Quartus II RTL viewer, find out how quartus II software synthesized your circuit.

Part2               8-bit synchronous counter using Q <+1

Circuit description

The functionality of the circuit is the same as part 1. The counter is accomplished using the statement: Q <= Q+1;

[prelab: complete the following Verilog code)]

            module lab3_part2(SW, KEY, HEX1, HEX0);

                        input [1:0] SW;

                        input [0:0] KEY;

                        output

                        // always block for counter

                        // instantiate seg7 twice

            endmodule

Implementation

_______Create a new project.

_______Write Verilog files (lab3_part2.v,  seg7.v) required by the above description.

_______Download DE2_pin_assignments.qsf from altera website.

_______In Quartus II, select assignments à import assignments, choose DE2_pin_assignments.qsf in the file box.

_______Compile your design.

Toolsà programmer, download the circuit into FPGA, and test the functionality.

_______Using Quartus II, find out how many logic elements (LEs) are used to implement your circuit.

_______Using Quartus II RTL viewer, find out how quartus II software synthesized your circuit.

Part4               a simple timer

Circuit Description

The circuit, driven by a 50MHz clock (CLOCK_50) (on-board), will display two-digit hexadecimal number on two 7-seg displays HEX1 and HEX0. The circuit consists of 3 parts: 1) 1 Hz clock signal generator; 2) 8-bit binary counter with reset (SW[0]) and enable (SW[1]); and 3) binary-seg decoder (seg7.v in lab2).

The Verilog code for a frequency divider is provided as follows:

module clock(input cclk, input[31:0] clkscale, output reg clk);

reg[31:0] ;

            always@(posedge cclk)

                        begin

                                    +1;

                                                if(clkq>)

                                                            begin

                                                                        clk=~clk;

                                                                        ;

                                                            end

                        end

endmodule

The frequency of output clk is equal to the frequency of input cclk divided by (2*clkscale). For example, if cclk frequency is 50MHz, clkscale should be 25,000,000 to generate 1Hz clk.

Your Verilog file will instantiate the module clock and seg7 (see lab2), and also include statements for 8-bit binary counter with reset, enable and clk (1Hz) as inputs.

[prelab: complete the following Verilog code]

            module lab3_part3(SW, CLOCK_50, HEX1, HEX0);

                        //SW[1]: enable (high active)

                        //SW[0]: resetn (low active)

                        input [1:0] SW;

                        input CLOCK_50;

                        output

                        // instantiate module clock

                        // always block for counter

                        // instantiate seg7 twice

            endmodule

Implementation

_______Create a new project.

_______Write Verilog files (lab3_part4.v, clock.v,  seg7.v (the one in lab2) ) required by the above description.

_______Download DE2_pin_assignments.qsf from altera website.

_______In Quartus II, select assignments à import assignments, choose DE2_pin_assignments.qsf in the file box.

_______Compile your design.

Toolsà programmer, download the circuit into FPGA, and test the functionality by change SW[1] and SW[0] values.