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Write a testbench stimulus for the below 8-bit Shift-Left Register with Positive-Edge SHIFTEN, Serial In and Serial Out. Start with all ones after...
Write a testbench stimulus for the below 8-bit Shift-Left Register with Positive-Edge SHIFTEN, Serial In and Serial Out. Start with all ones after the 8th=bit shifted to the left all zeros.module left_shifter(SHIFTEN, DIN, DOUT);input SHIFTEN,DIN;output DOUT;reg [7:0] tmp;always @(posedge SHIFTEN)begintmp <= tmp << 1;tmp[0] <= DIN;endassign DOUT = tmp[7];The iSim simulation should show:initiate inputsSHIFTEN = 0;DIN = 0;// Wait 100 ns for global reset to finish#20then it should start:DIN=8'b11111111after first posedge SHIFTENDOUT=8'b11111110after 2nd posedge SHIFTENDOUT=8'b11111100Please see attached example waveform, by the way, I don't know if the original verilog code can perform what I'm expecting.Need help Mr. SW_Wizard
