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QUESTION

Consider the following MIPS code segment . ( Remember MIPS memory size is 4 GB . ) Cache capacity is amp; words , Black size : 2 words , N = 1 ....

Can you help me for this kind of cache question. (LRU = Least Recently Used)

Consider the following MIPS code segment . ( Remember MIPS memory size is 4 GB . ) Cache capacity is &amp; words , Black size : 2 words , N = 1 .addi5to , 50 , 51010 17 :DECSto , 50 , doneIW5+1 , 0x 24 ( 50)IW5+ 2 , 0x 2 0 ( 50 )Iw513 , 0x 28 (50)addiSto , Sto , - 1loopdone !a . In the following table indicate the type of miss , if any : Compulsory , Conflict , Capacity .InstructionIteration NO .1234Iw 5+1 , 0x 24 ( 50 )IW 5 + 2 , 0 X 2 0 / 50 )Iw 5 +3 , 0x 28 ( 50 )b . What is the total cache memory size in number of bits ?&quot; Include the V bit your calculations . Show the details of your calculation .*C. State the number of AND and OR gates , EQUALITY COMPARATORS and MULTIPLEXER'S needed to implement the cache memory . No drawing is needed .Consider the above MIPS cade segment . The cache capacity is 2 words , block size is I word . There is only 1 set . The block replacement policy is LAU .a . In the following table indicate the type of miss , if any : Compulsory , Conflict , Capacity .InstructionIteration NO .Iw 5+1 , 0 x 24 150)IW St 2 , 0 x 2 0 1 50 )IW. 5+3 , 0 x 28 1 50 )6 . How many bits are needed for the implementation of LRU policy ?&quot; What is the total cache memory size in number of bits ? Include the V bit and the bit ( 5 ) used for LA'L in your calculations . Show the details of your calculation .C . State the number of AND and OR gates , EQUALITY COMPARATOR'S and MULTIPLEXER'S needed to implement the cache memory . No drawing is needed .